In recent years, there have been great advancements in the speed, power, and complexity of integrated circuits, such as application specific integrated circuit (ASIC) chips, random access memory (RAM) chips, microprocessor (uP) chips, and the like. These advancements have made possible the development of system-on-a-chip (SOC) devices. A SOC device integrates into a single chip many of the components of a complex electronic system, such as a wireless receiver (i.e., cell phone, a television receiver, and the like). SOC devices greatly reduce the size, cost, and power consumption of the system.
SOC devices typically employ one or more shared data buses to transfer information between their various subsystems. Examples of these include commercial standards, such as ARM's AMBA bus, and National Semiconductor's Geodelink Bus, as well as a variety of other proprietary solutions. In most of these systems, each device coupled to the data bus is capable of acting as a bus master. Any data bus (or communication bus) that has multiple masters must also contain a bus arbiter that grants bus access to a single requester in the event of request conflicts.
There are many algorithms for determining which of multiple requesting devices is given priority to act as bus master. Examples include fixed priority, random, round-robin, and the like. However, it is difficult to determine in advance the best algorithm for a given application. In many instances, the quality of the arbitration algorithm depends on the program code that is being executed. In fact, different portions of the code of the same program may require different arbitration algorithms in order to produce the most efficient results.
As a result, many arbiter implementations are little more than a best-guess estimate of the optimum arbitration algorithm. If the arbitration algorithm proves to be unacceptable after the design is implemented in silicon, the integrated circuit must be re-designed. This is a costly and ineffective approach.
Therefore, there is a need in the art for improved bus architectures that are capable of implementing the optimum arbitration algorithm for a wide variety of applications. In particular, there is a need for a bus arbiter that implements adaptable arbitration algorithms. More particularly, there is a need for a bus arbiter that implements a reprogrammable algorithm that may be changed during execution of an application program.